Toshiba is continuing their series of product announcements featuring their new 64-layer 3D TLC NAND flash memory. With the client SSD for OEMs segments covered by the XG5, BG3 and SG6 and with the TR200 covering the retail SATA market, Toshiba now turns to the enterprise SSD market with a new generation of NVMe and SAS SSDs. The PM5 SAS SSD and CM5 NVMe SSD are based on a new generation of SSD controllers that use the same architecture for both NVMe and SAS, allowing the two product families to share several key features.
The PM5 SAS SSD sets new records by offering capacities of up to 30.72 TB in a 2.5" form factor, and sequential transfer speeds of up to 3350 MB/s (reads) thanks to support for four-port SAS MultiLink. SAS has always supported dual-port drives, with the two ports either used in a failover configuration for high availability or bonded for high throughput. When SAS devices were still at 6Gbps there was serious discussion of going beyond two ports per drive and backwards-compatible connectors were standardized, but 12Gbps SAS won out as the preferred next step toward higher throughput. Now that NVMe SSDs using four or more PCIe lanes are providing heavy competition, MultiLink SAS has been dusted off and is being implemented on a SSD for the first time. Existing backplanes will need to be upgraded to physically provide the extra lanes, but otherwise the SAS ecosystem is ready to support 4-port MultiLink drives more or less transparently, since multi-lane/multi-path IO support is already ubiquitous.
The CM5 enterprise NVMe SSD will only offer capacities of up to 15.36TB but higher performance than its SAS cousin, including up to twice the random read performance. It supports the latest and greatest NVMe features: scatter-gather lists and Controller Memory Buffer (CMB) for more efficient NVMe over Fabrics use, multiple namespaces and SR-IOV virtualization, and NVMe Management Interface. The CM5 is also previewing a new Persistent Memory Region (PMR) feature that is on track for standardization. The PMR feature appears be an extension of the Controller Memory Buffer feature. CMB allows a NVMe SSD to expose a portion of its DRAM for general-purpose use by other parts of the system. The most common use case so far is with NVMe over Fabrics (NVMeoF) where an RDMA-capable NIC can store data and queued commands straight into the SSD's DRAM with peer-to-peer DMA, eliminating a round-trip to the CPU's DRAM. PMR envisions a different use for the SSD's DRAM by ensuring the buffer's contents are saved to the flash in the event of power loss. This allows the host system to treat the buffer in much the same manner as a NVDIMM providing battery-backed DRAM. The performance of a single drive's PMR won't be competitive with a NVDIMM due to a PCIe x4 link being much slower than a DDR4 bus, but it will provide a small pool of persistent memory that is faster than the drive's block storage accessed through NVMe.
Both the PM5 and CM5 implement their host interface's respective standard for streams support, allowing I/O commands to be tagged according to which task they originate from. This allows the SSD to write each task's data to separate parts of the drive, which makes it easier to offer higher and more consistent performance and also can lead to much lower write amplification as data with similar lifetimes is physically grouped together instead of being interleaved within the same erase blocks. The PM5 and CM5 also both support TCG encryption and the relatively new Sanitize command to securely erase not just the flash but all other buffers on the drive, which was not ensured by previous erase methods.
The PM5 SAS SSD will be available in capacities from 800GB to 30.72TB, with endurance ratings of 1, 3, 5 and 10 Drive Writes Per Day (DWPD). The CM5 NVMe SSD will be available in capacities from 400GB to 15.36TB with endurance ratings of 1, 3 and 5 DWPD. Both drives use Toshiba's 64-layer TLC BiCS3 3D NAND and are currently sampling to select OEM customers. The timeline for wider availability has not been announced. The SSDs will be on display this week at Flash Memory Summit in Santa Clara, CA.
from AnandTech http://ift.tt/2wAASoj